1. Field of Invention
This invention relates generally to semiconductor memories and specifically to single-poly floating gate memory cells.
2. Description of Related Art
A single-poly non-volatile EEPROM cell includes only one polysilicon layer and is thus advantageous since the memory cell and its associated logic circuitry may be fabricated using the same semiconductor fabrication process. The single-poly cell includes a floating gate which overlies a channel region extending between source and drain regions of the memory cell. The single-poly cell includes a buried control gate that is capacitively coupled to the floating gate in a manner similar to that of an MOS capacitor. Although early single-poly memory cells were primarily fabricated using NMOS technology, recent advances in the semiconductor industry have led to the development of a PMOS single-poly floating gate memory cell such as, for instance, that disclosed in U.S. Pat. No. 5,736,764 issued Apr. 7, 1998 to Chang, entitled "PMOS Flash EEPROM Cell with Single Poly" and assigned to Programmable Microelectronics Corporation of San Jose, Calif.
FIGS. 1 and 2A-2C illustrate a PMOS single-poly memory cell of the type disclosed in the Chang patent. The cell 10 is formed in an N-well 12 provided within a P-type substrate 14, and includes a P-channel programming transistor 16 and a P-channel select transistor 18. P+ diffusion region 20 serves as the source of programming transistor 16, P+ diffusion region 22 serves as both the drain of programming transistor 16 and the source of select transistor 18, and P+ diffusion region 24, which is coupled to a bit line BL, serves as the drain of select transistor 18. Poly-silicon gates 26 and 28 serve as the floating gate and select gate, respectively, of cell 10.
A P-type buried diffusion layer 36 serves as the control gate of cell 10. A contact region 38 is opened in floating gate 26 and in a layer of oxide 40 interposed between floating gate 26 and control gate 36 to enable electrical contact with buried control gate 36. A layer of oxide 40 is provided between floating gate 26 and P diffusion region 36. Application of a bias voltage to control gate 36 enhances a channel 30 extending between source 20 and drain 22 of programming transistor 16, and the application of a bias voltage to select gate 28 enhances a channel 32 extending between source 22 and drain 24 of select transistor 18. Together, floating gate 26 and control gate 36 form an MOS capacitor in a manner similar to that of conventional N-channel EEPROM cells.
The cell 10 is programmed by injecting electrons into the floating gate 26 from a depletion layer proximate drain 22. The resultant accumulation of negative charge on the floating gate 26 moves the threshold voltage of the cell 10 to a more positive voltage. The cell 10 is erased by electron tunneling from the floating gate 26 into channel 30, source 20, and drain 22, which returns the threshold voltage of the programming transistor 16 of cell 10 to its erased value. To read cell 10, a voltage differential is applied between P+ source 20 and P+ drain 22, and a suitable read voltage is applied to the control gate 36. The cell 10 conducts a channel current during read operations only if the floating gate 26 is charged, i.e., only if the cell 10 is programmed. For a more detailed discussion of PMOS single-poly floating gate memory cells, see also U.S. Pat. No. 5,761,121 issued Jun. 2, 1998 to Chang entitled "PMOS single-poly non-volatile memory structure," and U.S. Pat. No. 5,841,165 issued Nov. 24, 1998 to Chang and entitled "PMOS Flash EEPROM Cell with Single Poly."
PMOS floating gate memory cells such as the cell 10 are advantageous over NMOS floating gate memory cells in several respects. For example, since PMOS transistors exhibit higher gate currents than do NMOS transistors, PMOS floating gate memory cells use lower programming voltages than do NMOS floating gate memory cells. Further, since these lower programming voltages exhibit lower junction voltages, the PMOS cell size is not as limited by junction breakdown as is NMOS cell size. In addition, since a read current flows through a PMOS floating gate memory cell only when the floating gate is charged, PMOS cells do not suffer from read disturb problems characteristic of NMOS floating gate memory cells.
However, although advantageous in numerous respects over NMOS memory cells, the lower mobility of holes, as compared to that of electrons, undesirably limits the channel current of PMOS memory cells during read operations. This channel current limitation, in turn, undesirably limits the speed with which PMOS floating gate memory cells are read. Accordingly, it would be desirable for a single-poly floating gate memory cell to achieve programming advantages of PMOS memory cells without sacrificing memory cell access time.